1. Field of the Invention
The present invention relates to CMOS image sensors.
2. Related Technology
CMOS image sensors have wide application in consumer and industrial electronics. In general terms, CMOS image sensors are comprised of rows of pixels that supply analog pixel values. The analog pixel signals are read out row by row and converted to digital values. While consumer CMOS image sensor chips typically include only one or two analog to digital converters (ADCs), high speed CMOS image sensors utilize one ADC per column, or per several columns.
A simplified architecture of a conventional high speed CMOS image sensor is illustrated in FIG. 1. The image sensor includes a pixel array comprised of rows of pixel circuits 10. A row control signal supplied by a row decoder/driver 12 controls the operations performed by the pixel circuits in each row. Pixel circuits aligned in the same column share a common readout line 14. Signals from the pixel circuits are buffered or amplified by column readout circuits 16, digitized by ADCs 18, and stored in a static or dynamic RAM 20 that typically has parallel inputs and a serial output. The operation of the ADCs and the memory are controlled by a controller 22. Signals read from memory are amplified by sense amps 24 and supplied to buffers 26 that drive the signals to I/O pads.
Details of an ADC that may be used in the circuit of FIG. 1 are illustrated in FIG. 2. The output signal of a pixel circuit is supplied to an input 30 of the ADC by a buffer or amplifier. A reset capacitor 32 samples and holds a reset value received from the pixel circuit through a switch 34 responsive to a control signal SHR, thus providing a reset voltage at a first input node 36 of a comparator 38. A binary scaled sampling capacitor bank 40 samples and holds a pixel signal value received from the pixel circuit through a switch 38 responsive to a control signal SHS, thus providing a signal voltage at a second input node 42 of the comparator 38. Although not shown in FIG. 2, respective calibration circuits may be used to apply calibration values to the input nodes 36, 42, for example to provide black level calibration.
Conversion latches 44 control the application of reference values to the sampling capacitors 40, thus changing the voltage seen by the comparator 38 at the second input node 42. A binary scaled calibration capacitor bank 46 can also sample and hold a value from the input 30 of the ADC. Calibration latches 48 control the application of reference values to the capacitors of the calibration capacitor bank 46. The output 50 of the comparator is fed back to the conversion latches 44 and calibration latches 48.
In operation, a voltage corresponding to the pixel reset value is sampled and held at the first input node 36, and a voltage corresponding to the pixel signal is sampled and held at the second input node 42. The conversion latches 44 maintain a low ADC reference voltage on the bottom plates of the sampling capacitors 40 during sampling of the pixel signal. After the pixel signal is sampled, logic associated with the conversion latches 44 causes high voltages to be applied sequentially to the bottom plates of the capacitors in the sampling capacitor bank 40. Initially a high ADC reference voltage is applied to the bottom plate of the largest capacitor in the sampling capacitor bank 40. The resulting potential at the second input node 42 is compared to the reset value at the first input node 36 to generate a comparator 38 output value. If the potential at the second input node 42 is greater than the potential at the first input node 36, the comparator 38 output goes to 0 and the bottom plate of the capacitor is reset to low reference. Conversely, if the potential at the second input node 42 is less than the potential at the first input node 36, the comparator output goes to 1 and the bottom plate of the capacitor is maintained at high reference. The comparator output value generated by this comparison is the most significant bit of a binary word representing the value of the pixel signal sampled at the second input node 42. This process is repeated for all of the capacitors in the sampling capacitor bank 40 in order of decreasing size. The resulting string of comparator output values is a binary word representing the value of the pixel signal.
The high speed dynamic comparator 38 typically has some inherent offset between its inputs arising from the nonideal components of the comparator. The exact offset is individual for each ADC and therefore varies from column to column, producing artifacts in the sampled image. To compensate these offsets, a calibration procedure is performed in the ADC prior to operation using the calibration latches 48 and the calibration capacitor bank 46. The size of the capacitors in the calibration capacitor bank 46 can be smaller than those of the sampling capacitor bank 40 because the comparator offset is typically less than 10% of the full ADC range. The calibration procedure is performed using the offset value of the comparator as the sampled signal and results in settings of static memories associated with the individual calibration latches 48 that compensate the offset by selectively charging the capacitors of the calibration capacitor bank 46. The calibration procedure may be performed on power-up.
While this circuit can reduce ADC offset, the offset is typically not removed completely, and so column-to-column nonuniformity of ADCs remains. Further, in ADC circuits of the type illustrated in FIG. 2, the calibration capacitor bank 46 and calibration latches 48 may occupy up to 40% of the circuit area. This is an undesirable amount of space to devote to the calibration portion of the circuit